The present disclosure relates generally to interior pinning for large synthesis macro blocks and, more specifically, to a hierarchically aware interior pinning.
Large Synthesis Blocks (LBS) are able to create pinning solutions that are best for their own internal logic, while their hierarchical parents are able to create a pinning solution best suited for its needs.
Particularly, internal information and specifications about the child level architecture of the internal portion of a macro block can be collected and used to select a pinning solution that complements the particular internal structure of the macro block. For example, pins can be placed that allow for internal reduction of wire length and usage as well as improved signal transmittance speed. Alternatively, when connecting one macro block to another macro block or to other devices at a parent level there are provided methods and systems that allow for pinning solutions to be implemented that provide benefits and connection solutions that take into account consideration and information related to the parent level. For example, a macro block may adjust edge pinning to best connect that macro to other macros or devices on an integrated circuit. Thus, child consideration can be taken into account for the internal pinning and then after that is complete one can then provide an additional layer of edge pinning and wiring adjustments to potentially help connect with the parent layer
However, although there are a multiple of each type of pinning approaches known, there is not a balancing provided between the two but rather one must select between one or the other or one and then the other. Accordingly, there is a desire for an approach and design that can bridge the gap to create a solution that takes both the child and parent's needs into consideration before computing a pinning solution.